1. Field of the Invention
The present invention relates to a technical field of a phase locked state detecting apparatus and an information processing apparatus, particularly to a technical field of a phase locked state detecting apparatus for detecting a phase locked state of a signal which is phase controlled by a phase locked loop (PLL) circuit, and an information processing apparatus including the phase locked state detecting apparatus.
2. Description of Related Art
In recent years, an audio system has generally spread in which an information reproduction apparatus for reproducing music information from a compact disc (CD) is directly connected to an amplifier for amplifying and outputting the reproduced music information via a serial bus or another bus, and the reproduced music information is outputted to the outside via the amplifier.
In the amplifier in the audio system constituted as described above, a reference clock signal is generated based on time information transmitted with the reproduced music information. Then, a processing clock signal for use in a reproduction processing in the amplifier is set to a phase locked state based on the reference clock signal. The phase locked state means a state in which a phase of the reference clock signal accurately agrees with a phase of the processing clock signal. The processing clock signal maintaining this state is used to perform a necessary reproduction processing.
Moreover, this constitution accurately matches properties in data transmission of the information reproduction apparatus to those of the amplifier. For example, it matches properties of time information of the information reproduction apparatus to those of the amplifier. Therefore, while the information reproduction apparatus transmits the reproduced music information to the amplifier, it can amplify and output the reproduced music information.
In the conventional bus, however, depending on a bus type, when the information processing apparatus is newly connected to the bus, or when the connected information processing apparatus is disconnected from the bus, there may be cases where an initialization processing of temporarily initializing the information processing apparatus connected to the bus, and subsequently setting a new connection. For example, the initialization processing sets an information processing apparatus number for information transmission in the bus, or sets one information processing apparatus to generally control the information processing apparatuses interconnected via the bus with respect to the information transmission using the bus.
In this case, depending upon the bus type, the initialization processing includes an initialization processing requiring a long time for updating all connections in the information processing apparatuses connected to the bus (hereinafter referred to as long bus reset). The initialization processing also includes a short time initialization processing for performing the initialization processing similar to that of the long bus reset (hereinafter referred to as short bus reset).
On the other hand, the initialization processing is performed for the new connection of the information processing apparatus, even if the reproduction processing is executed in the amplifier. In this case, there is a problem that the music information being subjected to the reproduction processing is temporarily interrupted.
The present invention has been developed to solve the aforementioned problem, and an object thereof is to provide a phase locked state detecting apparatus for accurately detecting whether or not a phase locked state is canceled in an information processing apparatus connected to a bus and for minimizing interruption of an information processing when the aforementioned initialization processing is started during execution of the information processing in the information processing apparatus, and an information processing apparatus including the phase locked state detecting apparatus.
The above object of the present invention can be achieved by a phase locked state detecting apparatus in accordance with the present invention. The phase locked state detecting apparatus detects a phase locked state of a processing clock signal generated by a phase locked loop and used in an information processing. The phase locked state detecting apparatus includes: a comparing device for comparing a phase of a reference clock signal as the reference for controlling a phase of the processing clock signal by the phase locked loop with a phase of the processing clock signal and generating a comparison signal; a detecting device for detecting a change of frequency of the processing clock signal and generating a detecting signal; a first determining device for determining on the basis of the comparison signal whether or not the processing clock signal is in the phase locked state with respect to the reference clock signal, based on; and a second determining device for determining on the basis of the detecting signal whether or not the phase locked state is canceled after the first determining device determines that the processing clock signal is in the phase locked state.
According to the phase locked state detecting apparatus of the present invention, a result of phase comparison of the reference clock signal with the phase of the processing clock signal is used to determine whether or not the processing clock signal is in the phase locked state, and it is subsequently determined in accordance with a change of frequency of the processing clock signal whether or not the phase locked state is canceled. Therefore, in accordance with the change of the frequency (i.e., a frequency which does not follow even a change of the reference clock signal for a remarkably short time and does not quickly fluctuate) of the processing clock signal generated by a phased lock loop, it is determined whether or not the phase locked state is canceled. Therefore, even when there is a change of the reference clock signal for the remarkably short time, it is not determined that the phase locked state is canceled. The processing in which the processing clock signal in the phase locked state is used can be continued.
Moreover, the result of the phase comparison is used to determined whether or not the processing clock signal is in the phase locked state, and subsequently it is determined based on the change of the frequency of the processing clock signal itself whether or not the phase locked state of the processing clock signal is canceled. Therefore, it can accurately be detected whether or not the processing clock signal is in the phase locked state.
In one aspect of the phase locked state detecting apparatus of the present invention, the first determining device determines on the basis of the comparison signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when a difference between the phase of the reference clock signal and the phase of the processing clock signal continues to be not more than a preset value for a preset period, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when a state of the difference being not more than the value does not continue for the period.
According to this aspect, it can securely be determined whether or not the processing clock signal is in the phase locked state.
In another aspect of the phase locked state detecting apparatus of the present invention, the second determining device determines on the basis of the detecting signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when the change of the frequency of the processing clock signal is less than a preset threshold value, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when the change is not less than the threshold value.
According to this aspect, only the processing clock signal can be used to securely determine whether or not the processing clock signal is in the phase locked state.
The above object of the present invention can be achieved by an information processing apparatus in accordance with the present invention. The information processing apparatus includes the phase locked state detecting apparatus for detecting a phase locked state of a processing clock signal generated by a phase locked loop and used in an information processing. The phase locked state detecting apparatus is provided with: a comparing device for comparing a phase of a reference clock signal as the reference for controlling a phase of the processing clock signal by the phase locked loop with a phase of the processing clock signal and generating a comparison signal; a detecting device for detecting a change of frequency of the processing clock signal and generating a detecting signal; a first determining device for determining on the basis of the comparison signal whether or not the processing clock signal is in the phase locked state with respect to the reference clock signal, based on; and a second determining device for determining on the basis of the detecting signal whether or not the phase locked state is canceled after the first determining device determines that the processing clock signal is in the phase locked state. The information processing apparatus is provided with: a phase comparing device for detecting a phase difference between the reference clock signal and the processing clock signal and outputting a phase difference signal, being included in the phase locked loop; a filter device for subjecting the outputted phase difference signal to a predetermined filter processing and outputting a filter signal, being included in the phase locked loop; a generating device for generating an oscillation clock signal based on the outputted filter signal, being included in the phase locked loop; a frequency division device for dividing a frequency of the generated oscillation clock signal, generating the processing clock signal and outputting the processing clock signal to the phase locked state detecting apparatus and the phase comparing device, being included in the phase locked loop; and a processing device using the processing clock signal in the phase locked state with respect to the reference clock signal to perform an information processing based on a result of the determination in the phase locked state detecting apparatus.
Therefore, the processing clock signal which is in the phase locked state can be used to accurately perform the necessary information processing.
Moreover, even when the reference clock signal changes only for the remarkably short time, the information processing using the processing clock signal in the phase locked state can be continued.
In one aspect of the information processing apparatus of the present invention, the information processing is a reproduction processing of audio information inputted from the outside.
According to this aspect, the processing clock signal which is in the phase locked state can be used to accurately perform a necessary audio information reproduction processing.
Moreover, even when the reference clock signal changes only for the remarkably short time, the reproduction processing using the processing clock signal in the phase locked state can be continued.
In another aspect of the information processing apparatus of the present invention, the first determining device determines on the basis of the comparison signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when a difference between the phase of the reference clock signal and the phase of the processing clock signal continues to be not more than a preset value for a preset period, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when a state of the difference being not more than the value does not continue for the period.
According to this aspect, According to this aspect, it can securely be determined whether or not the processing clock signal is in the phase locked state.
In another aspect of the information processing apparatus of the present invention, the second determining device determines on the basis of the detecting signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when the change of the frequency of the processing clock signal is less than a preset threshold value, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when the change is not less than the threshold value.
According to this aspect, According to this aspect, only the processing clock signal can be used to securely determine whether or not the processing clock signal is in the phase locked state.
The above object of the present invention can be achieved by a phase locked state detecting method, in accordance with the present invention, for detecting a phase locked state of a processing clock signal generated by a phase locked loop and used in an information processing. The phase locked state detecting method includes: a comparing process of comparing a phase of a reference clock signal as the reference for controlling a phase of the processing clock signal by the phase locked loop with a phase of the processing clock signal and generating a comparison signal; a detecting process of detecting a change of frequency of the processing clock signal and generating a detecting signal; a first determining process of determining on the basis of the comparison signal whether or not the processing clock signal is in the phase locked state with respect to the reference clock signal, based on; and a second determining process of determining on the basis of the detecting signal whether or not the phase locked state is canceled after the first determining device determines that the processing clock signal is in the phase locked state.
According to the phase locked state detecting method of the present invention, a result of phase comparison of the reference clock signal with the phase of the processing clock signal is used to determine whether or not the processing clock signal is in the phase locked state, and it is subsequently determined in accordance with a change of frequency of the processing clock signal whether or not the phase locked state is canceled. Therefore, in accordance with the change of the frequency (i.e., a frequency which does not follow even a change of the reference clock signal for a remarkably short time and does not quickly fluctuate) of the processing clock signal generated by a phased lock loop, it is determined whether or not the phase locked state is canceled. Therefore, even when there is a change of the reference clock signal for the remarkably short time, it is not determined that the phase locked state is canceled. The processing in which the processing clock signal in the phase locked state is used can be continued.
Moreover, the result of the phase comparison is used to determined whether or not the processing clock signal is in the phase locked state, and subsequently it is determined based on the change of the frequency of the processing clock signal itself whether or not the phase locked state of the processing clock signal is canceled. Therefore, it can accurately be detected whether or not the processing clock signal is in the phase locked state.
In one aspect of the phase locked state detecting method of the present invention, the first determining process determines on the basis of the comparison signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when a difference between the phase of the reference clock signal and the phase of the processing clock signal continues to be not more than a preset value for a preset period, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when a state of the difference being not more than the value does not continue for the period.
According to this aspect, it can securely be determined whether or not the processing clock signal is in the phase locked state.
In another aspect of the phase locked state detecting method of the present invention, the second determining process determines on the basis of the detecting signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when the change of the frequency of the processing clock signal is less than a preset threshold value, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when the change is not less than the threshold value.
According to this aspect, only the processing clock signal can be used to securely determine whether or not the processing clock signal is in the phase locked state.
The above object of the present invention can be achieved by an information processing method, in accordance with the present invention, including the phase locked state detecting method for detecting a phase locked state of a processing clock signal generated by a phase locked loop and used in an information processing. The phase locked state detecting method includes: a comparing process for comparing a phase of a reference clock signal as the reference for controlling a phase of the processing clock signal by the phase locked loop with a phase of the processing clock signal and generating a comparison signal; a detecting process for detecting a change of frequency of the processing clock signal and generating a detecting signal; a first determining process for determining on the basis of the comparison signal whether or not the processing clock signal is in the phase locked state with respect to the reference clock signal, based on; and a second determining process for determining on the basis of the detecting signal whether or not the phase locked state is canceled after the first determining process determines that the processing clock signal is in the phase locked state. The information processing method includes: a phase comparing process for detecting a phase difference between the reference clock signal and the processing clock signal and outputting a phase difference signal in the phase locked loop; a filter process for subjecting the outputted phase difference signal to a predetermined filter processing and outputting a filter signal in the phase locked loop; a generating process for generating an oscillation clock signal based on the outputted filter signal in the phase locked loop; a frequency division process for dividing a frequency of the generated oscillation clock signal, generating the processing clock signal and outputting the processing clock signal so as to be used for the phase locked state detecting process and the phase comparing process in the phase locked loop; and a processing process using the processing clock signal in the phase locked state with respect to the reference clock signal to perform an information processing based on a result of the determination of the first determining process or the second determining process.
Therefore, the processing clock signal which is in the phase locked state can be used to accurately perform the necessary information processing.
Moreover, even when the reference clock signal changes only for the remarkably short time, the information processing using the processing clock signal in the phase locked state can be continued.
In one aspect of the information processing method of the present invention, the information processing is a reproduction processing of audio information inputted from the outside.
According to this aspect, the processing clock signal which is in the phase locked state can be used to accurately perform a necessary audio information reproduction processing.
Moreover, even when the reference clock signal changes only for the remarkably short time, the reproduction processing using the processing clock signal in the phase locked state can be continued.
In another aspect of the information processing method of the present invention, the first determining device determines on the basis of the comparison signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when a difference between the phase of the reference clock signal and the phase of the processing clock signal continues to be not more than a preset value for a preset period, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when a state of the difference being not more than the value does not continue for the period.
According to this aspect, According to this aspect, it can securely be determined whether or not the processing clock signal is in the phase locked state.
In another aspect of the information processing method of the present invention, the second determining process determines on the basis of the detecting signal that the processing clock signal is in the phase locked state with respect to the reference clock signal when the change of the frequency of the processing clock signal is less than a preset threshold value, and determines that the processing clock signal is not in the phase locked state with respect to the reference clock signal when the change is not less than the threshold value.
According to this aspect, According to this aspect, only the processing clock signal can be used to securely determine whether or not the processing clock signal is in the phase locked state.